This application claims the priority of Korean Patent Application No. 2003-74675, filed on Oct. 24, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a switching circuit, and more particularly, to a pass gate circuit.
2. Description of the Related Art
In general, a pass gate circuit is used in various parts of a semiconductor memory device in which switching operations are needed. For example, a pass gate circuit can be used in a data output circuit of a semiconductor device that includes a latch circuit. A pass gate circuit responds to a predetermined control signal by being turned on/off, and when turned on, receives and outputs input signals. An example of a latch circuit including a pass gate circuit is disclosed in U.S. Pat. No. 5,939,915.
An example of a conventional pass gate circuit is shown in FIG. 1. Referring to FIG. 1, the pass gate circuit 10 includes a switching unit 20 and a latch unit 30. The switching unit 20 includes a transmission gate 21 and an inverter 22 and the latch unit 30 includes inverters 31 and 32. The transmission gate 21 turns on or off in response to an external control signal (CTL).
The conventional pass gate circuit 10 with the above-described structure operates unstably when the level of the input signal (IN) and the level of the control signal (CTL) change at the same time. FIG. 2 illustrates an example in which the level of the input signal (IN) and level of the control signal (CTL) change at the same time. Referring to FIG. 2, when the input signal (IN) changes from a high level to a low level the control signal also changes from a high level to a low level. The transmission gate 21 of the pass gate circuit 10 is turned on when the control signal (CTL) is at a high level and is turned off when the control signal (CTL) is at a low level.
Ideally, the level of the output signal (OUT) of the pass gate circuit 10 changes to the same level as the input signal (IN) as shown in the portion of the signal OUT indicated by “A”. The pass gate circuit 10 operates normally when the level of the input signal (IN) changes at a time when there is no level change of the control signal.
However, the pass gate circuit 10 operates unstably and abnormally when the level of the input signal (IN) and the level of the control signal (CTL) change at the same time. That is, as in the case illustrated by “B” which indicates the level of the output signal (OUT) of the pass gate circuit 10, only after a predetermined delay does the level of the output signal (OUT) become identical with the level of the input signal (IN). In addition, as indicated by “C” the pass gate circuit 10 can output an incorrect output signal (OUT), which is different from the input signal (IN). Such problems are aggravated by shorter switching periods of the pass gate circuit 10.
Also, when such a pass gate circuit is used in a self-refresh circuit of a semiconductor memory device, which requires precise operation, the self-refresh circuit can carry out an incorrect operation due to unstable operation of the pass gate circuit.